The invention relates to the fabrication of integrated circuit (IC) devices, particularly to dielectric materials, and more particularly to the fabrication of an interconnect structure which includes a low-k or ultralow-k interlevel dielectric layer (ILD).
Semiconductor devices are typically joined together to form useful circuits using interconnect structures comprising conductive materials (e.g., metal lines) such as copper (Cu) or aluminum (Al) and dielectric materials such as silicon dioxide (SiO2). The speed of these interconnects can be roughly assumed to be inversely proportional to the product of the line resistance (R), and the capacitance (C) between lines. To reduce the delay and increase the speed, it is desirable to reduce the capacitance (C). This can be done by reducing the dielectric constant, k, of the dielectric material in the interlevel dielectric layers (ILDs).
A common dielectric material for use in an interlevel dielectric layer (ILD) is silicon dioxide (SiO2, also referred to simply as “oxide”). Oxide has a dielectric constant k of at least 3.85 typically 4.1-4.3, or higher. Air has a dielectric constant k of approximately 1.0. By definition, a vacuum (free space) has a dielectric constant k of 1.0.
“Low-k” dielectric materials are known, and are typically defined as materials having a dielectric constant k less than 3.85—in other words, less than that of oxide.
A variety of “low-k” materials are known, such as SiLK™, an organic polymer with k=2.65 sold by Dow Chemical., and Black Diamond™, a organosilicon glass with a dielectric constant, k, of 2.7 to 3.0, sold by Applied Materials.
Dielectric materials can also be categorized by how they are applied (deposited) on the surface of a semiconductor wafer—for example, by a vapor deposition process or by a spin-on deposition process. Chemical Vapor Deposition (CVD) is used to deposit both dielectric and conductive films via a chemical reaction that occurs between various gases in a reaction chamber. Plasma enhanced Chemical Vapor Deposition (PECVD) uses an inductively coupled plasma to generate different ionic and atomic species during the deposition process. PECVD typically results in a low temperature deposition compared to the corresponding thermal CVD process. Spin-on processes are used to deposit materials such as photoresist, and can also be used to deposit dielectric materials. A wafer is coated with material in liquid form, then spun at speeds up to 6000 rpm, during which the liquid is uniformly distributed on the surface by centrifugal forces, followed by a low temperature bake which solidifies the material.
Examples of CVD and PECVD low-k materials include:                Black Diamond™, a organosilicon glass (OSG) which is a Si—O—C—H type of material, with a dielectric constant k of 2.7 to 3.0 (e.g., 2.9), sold by Applied Materials Inc.        CORAL™, also an organosilicon glass (OSG) which is a Si—O—C—H type of material, with k of 2.7-3.0, sold by Novellus Systems, Inc.        fluorinated SiO2 glass, and amorphous C:F.        porous-Organo-silicate materials that is offered by a variety of vendors.        
Examples of spin-on low-k materials include:                BCB (divinylsiloxane bisbenzocyclobutene), sold by Dow Chemical.        SiLK™, an organic polymer with k=2.65, similar to BCB, sold by Dow Chemical.        NANOGLASS™, an inorganic porous polymer with k=2.2, sold by Honeywell        FLARE 2.0™ dielectric, an organic low-k poly(arylene)ether available from Allied Signal, Advanced Microelectronic Materials, Sunnyvale, Calif.        Inorganic materials such as spin-on glass (SOG), fluorinated silicon glass (FSG) and, particularly, methyl-doped porous silica which is referred to by practitioners of the art as black diamond, or BD.        Organo-silicate materials, such as JSR LKD 5109 (a spin-on material, Japan Synthetic Rubber)—Organic polymers (fluorinated or non-fluorinated), inorganic polymers (nonporous), inorganic-organic hybrids, or porous materials (xerogels or aerogels).        Materials in the parylene family of polymers, the polynapthalene family of polymers, or polytetrafluoroethylene.        
It is known that pores in dielectric materials can lower the dielectric constant. Low-k dielectric materials can typically be deposited ab initio either with or without pores, depending on process conditions. Since air has a dielectric constant of nearly 1, porous films exhibit reduced dielectric constants in contrast with the base material in which they are developed.
The use of low-k materials, with or without pores, is well known for use as Interlevel Dielectric Layer (ILD). Sometimes, materials having k<2.7 are referred to as “ultralow-k”.
Damascene, particularly dual damascene interconnect structures have received widespread application in recent years. They allow for high aspect ratio (i.e., tall, yet thin) conductive lines, hence greater interconnect densities. Generally, a dual damascene structure comprises a via etched through a first dielectric layer and a trench etched through a second, overlying dielectric layer, over-filling the via and trench with metal (usually copper) and then planarizing the resulting interconnect structure with chemical mechanical polishing (CMP). Before depositing copper, various other layers are deposited (e.g., barrier, liner, copper seed, plate). An example of a dual damascene structure is illustrated in U.S. Pat. No. 6,358,839.
Chemical Mechanical Polishing (CMP) is a key technology in the manufacture of high-density electronic circuits. The process uses advanced polishing techniques involving slurries—mixture of high-performance abrasives and chemicals. CMP is very important in the process for manufacturing a semiconductor device, for instance, shallow trench isolation (STI), planarization of interlayer dielectric (ILD), formation of embedded metal line, plug formation, formation of embedded capacitor, and the like. CMP involves rotating a wafer against a polishing pad under pressure in the presence of a slurry. Since the process of CMP is very well known in the art, including its essential components, it need not be discussed in much detail herein.
A problem with porous ultra-low-k materials, is that they are generally not compatible with CMP. Because of their porous nature these materials are innately soft, when compared to their bulk (non-porous) counterparts, which can give rise to problems during semiconductor processing, particularly during planarization by CMP.
For any dielectric materials—i.e., low-k and ultralow-k materials—that are inherently not compatible with CMP, it is known to provide a hard mask (HM) over the dielectric material to avoid polishing the dielectric material (act as a polish stop). Examples of hard mask materials are silicon carbides such as SiC, SiCN, SiCNH, SiCOH, SiCO, or SiCH. Often, the hard mask comprises an additional, overlying sacrificial layer of oxide which also forms part of the overall hard mask.
In a typical damascene process, when excess metal (i.e., metal overfilling the trench, typically copper (Cu)) is removed by CMP the lower HM remains in place, but will have been thinned by CMP, in some areas more than others, due to non-uniform pattern densities across the wafer. Some typical CMP slurries for performing Cu CMP are:                Abrasive (alumina, silica), plus        oxidizer (hydrogen peroxide, ferric nitrate), plus        additives (BTA, surfactants).        
A typical polish selectivity (ratio) for Cu CMP between the copper and the hard mask would be:Cu polish rate:SiCOH HM polish rate ˜25:1.
The ultralow K dielectric material for high performance interconnect structure usually requires a CMP hard mask on top of it to protect it from damage caused by CMP process. (The hard mask may also be important for sealing porous dielectric materials.) It is important that the CMP hard mask be retained uniformly after CMP process. This is usually a problem because of the pattern (of copper lines) density is not uniform on the chip.